Electronic devices, such as various image sensors and image processing equipments etc., which are under the necessity of converting analog signals into digital signals are required to do high speed processing of a large amount of data. As an A/D converter permitting to handle such processing, there has been known heretofore a pipeline type A/D converter configured by connecting cascade connected plural A/D converters to allow multiple A/D converting processing for one clock.
A conventional pipeline type A/D converter includes, e.g., a pipeline type A/D converter disclosed in Non-Patent Document 1.
Firstly, a description will be made to a configuration of the conventional general pipeline type A/D converter referring to the FIG. 10. FIG. 10 is a block diagram showing the configuration of the conventional general pipeline type A/D converter.
The pipeline type A/D converter 100 shown in FIG. 10 includes a sample-hold circuit 101, cascade connected k A/D converters 102 to 102-k, a memory 103, an arithmetic circuit 104, and a controller 105.
The sample-hold circuit 101 is for sampling and holding an analog signal Ain and for feeding the held analog signal Ain to a first A/D converter 102-1.
The A/D converters 102-1 to 102-k are cascade connected, perform an A/D conversion by the amount corresponding to resolution responsible for each A/D converter 102-1 to 102-k based on an analog signal input Vin to respective stages, and feed digital output signals dj (j=1, 2, . . . , k) of s-digit to a memory 103. Further, the A/D converters 102-1 to 102-k feed an analog signal Vout obtained in the respective stages from an analog output signal Ain the digital to analog converted result of the digital output signals dj to the following stage.
The memory 103 receives and stores the digital output signals dj of S-digit, determined by the k A/D converters 102-1 to 102-k. Namely, as a candidate of the memory 103, it may employ a semiconductor memory etc. which includes at least k addresses and can store S-bit data stored per one address.
The arithmetic circuit 104 synthesizes the digital output signals d stored in the memory 103 to calculate S-bit digital output signal Dout. A calculation method implemented in the arithmetic circuit 104 is as follows. Firstly, the most significant digit of dk and the least significant bit of dk-1 are added by the binary system. Secondly, based on this result, the most significant digit of dk-1 and the least significant bit of dk-2 are added in the same way by the binary system. After this, this operation is repeated and the least significant bit of d1 and the most significant bit of d2 are summed up lastly. Thus, the result obtained by adding the all dj is the digital output signal Dout.
The controller 105 is for generating switching element control signals φ1 and φ2 to electrically switch each switching element in the A/D converters 102-1 to 102-k to either of an electrically connected state or a disconnected state, in order to carry out the sampling and holding operations of the analog signal Vin, in synchronization with a master clock signal φ generated therein.
The A/D converters 102-1 to 102-k have the same circuit configuration configured by the same elements, so a description will be made to the circuit configuration of the A/D converter 102-1 by referring to FIG. 11.
FIG. 11 is a circuit diagram showing a circuit configuration of the A/D converter 102-1 when its resolution is 1.5 bit. The resolution of 1.5 bit implicates that a digital output signal output from the A/D converter 102-1 has three values.
The A/D converter 102-1 shown in FIG. 11 includes sample-hold switching elements 121-125, sample-hold capacitors 126 and 127, an operational amplifier 128, an A/D sub-converter 129, and a multiple value output circuit 130.
The sample-hold switching elements 121-125 are for switching an electrical connection state to either of the connected state or the disconnected state, in response to the switching element control signals φ1 and φ2 output from the controller 105 to carry out sampling and holding operations. The sample-hold switching elements 121, 122 are connected between an input terminal into which the analog signal Vin is input and input terminals of the sample-hold capacitors 126 and 127, respectively. The sample-hold switching element 123 is connected between output terminals of the sample-hold capacitors 126 and 127 and analog ground. The sample-hold switching element 124 is connected between an output terminal of the operational amplifier 128 and the input terminal of the sample-hold capacitor 126. The sample-hold switching element 125 is connected between an output terminal of the multiple-value output circuit 130 and the input terminal of the sample-hold capacitor 127. The above switching elements are each switched to the connected state when the switching element control signals φ1 and φ2 are in High level, and to the disconnected state when the switching element control signals φ1 and φ2 are in low level.
The sample-hold capacitors 126 and 127 are for charging and discharging an electrical charge corresponding to the sampled analog signal Vin, based on the reference voltage output from the multiple-value output circuit 130.
The non-inverting (+) input terminal of the operational amplifier 128 is connected to the analog ground, and the inverting (−) input terminal is connected with the sample-hold capacitors 126 and 127. The operational amplifier 128 is for amplifying a potential difference of signals input into the two input terminals.
The A/D sub-converter 129 is configured with two comparators (not shown) and is for converting the analog signal Vin into the digital output signals dj.
The multiple-value output circuit 130 is configured with multiple-value output switching elements 131 to 133. The switching elements 131 to 133 are connected between a voltage source for outputting of −Vref(V), 0V, and +Vref (V) that are prescribed voltages and an output terminal of the multiple-value output circuit 130, and is for switching the electrical connection state to either the connected state or the disconnected state based on the output result of the A/D sub-converter 129. The multiple-value output circuit 130 outputs one of reference voltages from −Vref(V), 0V, and +Vref(V), when the electrical connection state of the switching elements 131 to 133 are switched based on the digital output signal dj. Vref is a prescribed voltage determined with an input range of A/D conversion and 0 is a voltage of the analog ground.
Behavior of the A/D converter 102-2 includes a sampling operation phase and a holding operation phase. These sampling and holding operations are alternatively repeated.
At the sampling operation, the sample-hold switching elements 121 to 123 are switched to the connected state and the sample-hold switching elements 124 and 125 are switched to the disconnected state. The analog signal Vin input from the A/D converter 102-1 of the previous stage is sampled by the sample-hold capacitors 126 and 127. Moreover, after the analog signal Vin is subjected to an analog to digital conversion into one of −1, 0, and 1, the A/D sub-converter 129 outputs the analog signal Vin input from the A/D converter 102-1 of the previous stage. The multiple-value output circuit 130 outputs one of the reference voltages from −Vref(V), 0V, and +Vref (V) based on the output result of the A/D sub-converter 129.
At the holding operation, the sample-hold switching elements 121 to 123 are switched to the disconnected state and the sample-hold switching elements 124 and 125 are switched to the connected state. Then, a capacitor 126 is connected between the output terminal and the inverting terminal of the operational amplifier 128 to utilize it as a feedback element. Thereby, the voltage of the analog signal Vin is doubly amplified. Furthermore, the electrical connection state of one of the switching elements 131 to 133 is switched to the connected state depending on the output result of the A/D sub-converter 129, and one of −Vref(V), 0V, and +Vref(V) is output to the capacitor 127. Thereby, the analog signal Vout possible to be taken within the range of doubly amplified analog signal Vin falls within the input range of an A/D converter of the following stage. The analog signal Vout becomes the analog signal Vin of the A/D converter 102-2 connected to the following stage of the A/D converter 102-1.
Subsequently, a description will be made to a relationship between the input range of the analog signal Vin and the output range of the analog signal Vout of the A/D converter 102-1 referring to FIG. 12. FIG. 12 is a graph illustrating the relationship between the input range of the analog signal Vin and the output range of the analog signal Vout of the A/D converter 102-1.
The horizontal axis of the graph shown in FIG. 12 indicates voltage of the analog signal Vin input into the A/D converter 102-1 and the vertical axis indicates voltage of the analog signal Vout output from the A/D converter 102-1.
As shown by arrows in FIG. 12, the range of voltage the analog signal Vin can be taken is an input range of the A/D converter 102-1. Moreover, the range of voltage that the analog signal Vout can be taken within the input range of the analog signal Vin, is the output range of the A/D converter 102-1 i.e., the input range of the A/D converter 102-2.
As described above, the addition and subtraction of the reference voltage determined according to an output value of the A/D sub-converter 129 from the analog signal Vin doubly amplified by the A/D converter 102-1 limits the analog Vout of the A/D converter within the input range of the A/D converter of the following stage.
It is to be noted that, however, in the pipeline type A/D converter built in a number of electrical devices such as digital cameras etc., it needs to cancel an offset caused by signals from the outside or an internal offset potentially inherent in the pipeline type A/D converter itself. Thus, even the pipeline type A/D converter from which S-bit digital output signal Dout can be output, the converter needs to be capable of outputting a larger digital value by S+0.5 bits. Accordingly, in a certain A/D converter included in plural A/D converters of the pipeline type A/D converters, it is designed to have a larger input range than usual. Generally, it is often the case with the first A/D converter where the largest input range is available, the converter may take a larger input range is taken than usual. Hence, in the pipeline type A/D converter 100, a description will then be made to the case where the first A/D converter 102-1 is configured to take a larger input range than usual.
A description will next be made to the circuit of the A/D converter 102-1b where a larger input range than usual may be taken, by referring to FIG. 13. FIG. 13 is a circuit diagram showing a circuit configuration of the A/D converter 102-1b which is allowed to take the larger input range than usual.
The A/D converter shown in FIG. 13 is one in which the input range is expanded as an example by 1.5 times, and the number of output bits of the digital output signal Dout is increased by S+0.5 bits.
Differences between the A/D converter 102-1 shown in FIG. 11 and the A/D converter 102-1b shown in FIG. 13 are that the multiple-value output circuit 130 further includes three multiple-value output switching elements 131b to 133b, and the A/D converter 102-1b further includes sample-hold switching elements 122b and 125b and a sample-hold capacitor 127b. 
The sample-hold switching element 125b is connected, as with the sample-hold switching element 125, between the sample-hold capacitor 127b corresponding to the sample-hold capacitor 127 and the multiple-value output circuit 130.
The sample-hold capacitor 127b corresponds to the sample-hold capacitor 127, and is designed such that both terminals thereof are connected to the analog ground via the sample-hold switching elements 122b and 123 and an electrical charge is discharged to the analog ground for resetting it. That is, the sample-hold capacitor 127b does not sample or hold an electrical charge corresponding to the analog signal Vin and instead adds and subtracts the reference voltage output from the multiple-value output circuit 130 with 0V set as a reference.
The multiple-value output switching elements 131b to 133b are for switching, as with the multiple-value output switching elements 131 to 133, the electrical connection state based on the output result of the A/D sub-converter 129. The A/D sub-converter 129 includes four comparators (not shown) and is designed to be able to output one value from five values of −2, −1, 0, 1, and 2 depending on the analog signal Vin. Consequently, the multiple-value output circuit 130 can output two reference voltages, each including one of −Vref(V), 0V, and +Vref (V) based on the output result of the A/D sub-converter 129.
Even in the A/D converter 102-1b, the sampling operation and the holding operation are alternatively repeated by switching the electrical connection state of the respective switching elements in response to the switching element control signals φ1 and φ2, as with the A/D converter 102-1 shown in FIG. 11.
At the sampling operation, the sample-hold switching elements 121 to 123, 122b are switched to the connected state and the sample-hold switching elements 124, 125, 125b are switched to the disconnected state. The sample-hold capacitors 126 and 127 sample the voltage corresponding to the analog signal Vin. Further, the sample-hold capacitor 127b is reset to 0V.
At the holding operation, one of the multiple-value output switching elements 131 to 133 is connected to one of the multiple-value output switching elements 131b to 133b depending on the output result of the A/D sub-converter 129. Then, one of the reference voltages from −Vref(V), 0V, and +Vref (V) is respectively output to the sample-hold capacitors 127 and 127b. Thereby, two reference voltages are added to and subtracted from the doubly amplified analog signal Vin. Even when the expanded input range of the analog signal Vin is input into the A/D converter 102-1, the analog signal Vout output from the A/D converter 102-1 falls within the input range of the A/D converter 102-2 of the following stage.
Subsequently, a description will be made to a relationship between the input range of the analog signal Vin and the output range of the analog signal V out of the A/D converter 102-1b, by referring to FIG. 14. FIG. 14 is a graph illustrating a relationship between the input range of the analog signal Vin and the output range of the analog signal Vout of the A/D converter 102-1b. 
The horizontal axis of the graph shown in FIG. 14 indicates voltage of the analog signal Vin input into the A/D converter 102-1b, and the vertical axis thereof indicates voltage of the analog signal Vout output from the A/D converter 102-1b. 
As shown by arrows in FIG. 14, the input range of the A/D converter 102-1b is expanded by 1.5 times from an input-output characteristic as shown in FIG. 12. Specifically, the output range of the A/D converter 102-1b falls within the input range of the A/D converter 102-2. This means that the input range of the pipeline type A/D converter is expanded by the amount corresponding to bits processed by the A/D converter 102-1b. The first A/D converter 102-1b processes the most significant bit out of the S-bit digital output signal Dout. For this reason, when the input range of the first A/D converter 102-1b is expanded by 1.5 times, the whole input range of the pipeline type A/D converter 100 is expanded by 1.5 times, which enables increasing the digital output signal Dout to S+0.5 bits.
In FIG. 11, while the description has been made as to the A/D converter 102-1 of which resolution is 1.5 bits, the resolution is not necessarily limited to 1.5 bits.
FIG. 15 is a circuit diagram showing a circuit configuration of the A/D converter 102-1c of which resolution is 2.5 bits. The resolution of 2.5 bits implicates that a digital output signal output from the A/D converter 102-1c has seven values.
FIG. 15 is a circuit diagram configured with the same elements as those of the A/D converter 102-1 shown in FIG. 11. There are differences therebetween in that the resolution gets 2.5 times, so the amplification degree of the analog signal Vin gets four times. Specifically, the A/D converter 102-1c includes sample-hold switching elements 221 to 229, sample-hold capacitors 230 to 233, an A/D sub-converter 235, and the multiple-value output circuit 236 including 12 switching elements 237 to 245. The multiple-value output circuit 236 is designed to be able to output three reference voltages each including one of −Vref (V), 0V, and +Vref (V) based on the digital value determined according to the analog signal Vin output from the A/D sub-converter 235.
The sample-hold switching elements 221 to 229 are for switching an electrical connection state to either the connected state or the disconnected state to carry out the sampling and holding operations, in response to the switching element control signals φ1 and φ2. The sample-hold switching elements 221 to 224 are connected between input terminals for inputting the analog single Vin and input terminals of the sample-hold capacitors 230 to 233, respectively. The sample-hold switching element 225 is connected between output terminals of the sample-hold capacitors 230 to 233 and the analog ground. The sample-hold switching element 226 is connected between the output terminal of the operational amplifier 234 and the input terminal of the sample-hold capacitor 230. The sample-hold switching elements 227 to 229 are connected between output terminals of the multiple-value output circuit 236 and the input terminals of the sample-hold capacitors 231 to 233, respectively. The above respective switching elements are switched to the connected state when the switching element control signals φ1 and φ2 are in High level, and to the disconnected state when the switching element control signals φ1 and φ2 are in Low level.
At the sampling operation, the sample-hold switching elements 221 to 225 are firstly switched to the connected state and the sample-hold switching elements 226 to 229 are switched to the disconnected state. The analog signal Vin is sampled by the sample-hold capacitors 230 to 233. The A/D sub-converter 235 includes six A/D converters (not shown) which perform an A/D conversion of the analog signal Vin into one of seven values −3, −2, −1, 0, 1, 2, and 3 for thereafter outputting it. The multiple-value output circuit 236 outputs three reference voltages each including one of −Vref(V), 0V, and +Vref (V) based on the output result of the A/D sub-converter 235.
At the holding operation, the sample-hold switching elements 221 to 225 are switched to the disconnected state and the sample-hold switching elements 226 to 229 are switched to the connected state. A capacitor 230 is connected between an output terminal and an inverting input terminal of the operational amplifier 234 to use it as a feedback element. This amplifies the voltage of the analog signal Vin to four times thereof. Moreover, depending on the output result of the A/D sub-converter 235, one electrical connection state of each of the switching elements 237 to 239, 240 to 242, and 243 to 245 is switched to the connected state and one of −Vref(V), 0V, and +Vref(V) is output into each of the capacitors 231 to 233. Thereby, the analog signal Vout that can be taken within the range of the fourfold amplified analog signal Vin is made to fall within the input range of the A/D converter of the following stage. Then, the analog signal Vout becomes the analog signal Vin of the A/D converter connected in the following stage.
Then, a description will be made to a relationship between an input range of the analog signal Vin of the A/D converter 102-1c and an output range of the analog signal Vout, by referring to FIG. 16. FIG. 16 is a graph illustrating the relationship between the input range of the analog signal Vin and the output range of the analog signal Vout of the A/D converter 102-1c. 
The horizontal axis of the graph shown in FIG. 16 indicates voltage of the analog signal Vin input into the A/D converter 102-1c and the vertical axis thereof indicates voltage of the analog signal Vout output from the A/D converter 102-1c. 
As shown by arrows in FIG. 16, the range of voltage that the analog signal Vin can be taken becomes the input range of the A/D converter 102-1c. Within the input range of the analog signal Vin, the range of voltage that the analog signal Vout can be taken becomes the output range of the A/D converter 102-1c i.e., an input range of the A/D converter of the next stage.
As described above, adding and subtracting the reference voltage to be determined according to an output value of the A/D sub-converter 235, to and from the fourfold amplified analog signal Vin by the A/D converter 102-1c prevents the analog signal Vout of the A/D converter from exceeding the input range of the A/D converter of the following stage.
A description will then be made to a circuit of the A/D converter 102-1d in which a wider input range may be taken than usual, by referring to FIG. 17. FIG. 17 is a circuit diagram showing a circuit configuration of the A/D converter 102-1d in which a wider input range may be taken than usual.
The A/D converter 102-1d shown in FIG. 17 has an input range expanded as an example by 1.25 times, and the number of output bits of the digital output signal Dout is increased to S+0.25 bits.
There are differences between the A/D converter 102-1c shown in FIG. 15 and the A/D converter 102-1d shown in FIG. 17 in that the multiple-value output circuit 236 further includes three multiple-value output switching elements 243b to 245b, and the A/D converter 102-1d further includes sample-hold switching elements 224b and 229b and the sample-hold capacitor 233b. 
The sample-hold switching element 229b is connected between the sample-hold capacitor 233b corresponding to the sample-hold capacitor 233 and the multiple-value output circuit 236, as with the sample-hold switching element 229.
The sample-hold capacitor 233b is corresponds to the sample-hold capacitor 233 and both terminals thereof are connected to the analog ground via the sample-hold switching elements 224b and 225 to discharge an electrical charge to the analog ground for resetting it. That is, the sample-hold capacitor 233b does not sample or hold the electrical charge corresponding to the analog signal Vin, but adds and subtracts the reference voltage output from the multiple-value output circuit 236 with 0V set as reference.
The multiple-value output switching elements 243b to 245b are for switching an electrical connection state based on the output result of the A/D sub-converter 235, as with the multiple-value output switching elements 243 to 245. The A/D sub-converter 235 includes eight comparators (not shown) to perform an analog-digital conversion for one of nine values −4, −3, −2, −1, 0, 1, 2, 3, and 4 according to the analog signal Vin for outputting it. Thus, the multiple-value output circuit 236 is capable of outputting four reference voltages each including one of −Vref(v), 0V, and +Vref(V).
Even in the A/D converter 102-1d, the sampling operation and the holding operation are alternatively repeated by switching the electrical connection state of each switching element in response to the switching element control signals φ1 and φ2, as with the A/D converter 102-1c shown in FIG. 15.
At the sampling operation, the sample-hold switching elements 221 to 225, and 224b are switched to the connected state and the sample-hold switching elements 226 to 229, and 229b are switched to the disconnected state. An electrical charge corresponding to the analog signal Vin is sampled by the sample-hold capacitors 230 to 233. Additionally, the sample-hold capacitor 233b is reset to 0V.
At the holding operation, one of the multiple-value output switching elements 237 to 239, one of the multiple-value output switching elements 240 to 242, one of the multiple-value output switching elements 243 to 245, and one of multiple-value output switching elements 243b to 245b are switched to the connected state. Then, one reference voltage of −Vref(V), 0V, and +Vref (V) is output respectively to the sample-hold capacitors 231 to 233, and 233b. Thereby, even when four reference voltages are added to and subtracted from the fourfold amplified analog signal Vin so the input range of the analog signal Vin of the A/D converter 102-1d is made larger, the analog signal Vout output from the A/D converter 102-1d is made to fall within the input range of the A/D converter of the following stage.
Subsequently, a description will be made to a relationship between the input range of the analog signal Vin of the A/D converter 102-1d and the output range of the analog signal Vout, by referring to FIG. 18. FIG. 18 is a graph illustrating the relationship between the input range of the analog signal Vin of the A/D converter 102-1d and the output range of the analog signal Vout.
The horizontal axis of the graph shown in FIG. 18 indicates voltage of the analog signal Vin input into the A/D converter 102-1d and the vertical axis thereof indicates voltage of the analog signal Vout output from the A/D converter 102-1d. 
As shown by arrows in FIG. 18, the input range of the A/D converter 102-1d is expanded by 1.25 times from an input-output characteristic shown in FIG. 16. In this regard, the output range of the A/D converter 102-1d falls within the input range of the A/D converter of the following stage. This means that the input range of the pipeline type A/D converter is expanded by the amount corresponding to bits processed by the A/D converter 102-1d. The first A/D converter 102-1d is responsible for the most significant bit out of the S-bit digital output signals Dout. On this account, when the input range of the first A/D converter 102-1d is expanded by 1.25 times, the input range of the whole pipeline type A/D converter 100 expands by 1.25 times, thus increasing the digital output signal Dout to S+0.25 bits.